In order to direct high-voltages from the on-chip charge pumps to the appropriate Flash cell in an embedded Flash technology, special transistors over and above the standard logic CMOS transistors may be required which are robust in the face of such high voltages. These transistors may suffer from gate-induced drain leakage (GIDL) constraints in the off-state which may be avoided through offsetting the source/drain implants from the gate stack edge. Such offsetting may be accomplished through lithographic means and the accuracy of the offset may thus depend on the overlay of the lithographic process. A new way to provide offsetting is needed.